Design of Energy Efficicent CMOS Current Comparator

In high-speed high-resolution analog to digital converters, comparators have a key role in quality of performance. High power consumption and delay is one of the drawbacks of these circuits which can be reduced by using suitable architectures. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep sub-micron design technologies. Back to back inverter in the latch stage is replaced with dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparator. In this paper, a new low-voltage continuoustime current comparator is presented. The main idea is to use the voltage follower as a key element for the comparator input stage. This configuration delivers a very low input resistance, which is mandatory for current-mode applications. Previous reported current comparators present a high-speed response; nevertheless, only few are suitable for low-voltage applications. Simulations and experimental results using the complementary MOS 0.18-μm technology are presented to demonstrate the circuit feasibility.